A conventional SRAM (Static Random Access Memory) circuit has a one read/write circuit, in which a read port and a write port are in common. In this case, a port refers to an input/output interface for reading or writing data, a register for storing an address, a decoder for decoding an address, and a bit line and a word line to specify a position of an address. In the case of the one read/write circuit, reading and writing cannot be executed simultaneously. Also when data is read or written, an address position of reading or writing is determined using a common address decoder. Therefore the number of bits of an address used for reading and writing are the same.
On the other hand, an SRAM circuit having a plurality of ports has been proposed (e.g. see Non-patent Document 1).
A one read/two write SRAM circuit, which is an example of an SRAM circuit having a plurality of discrete ports, has one read port and two write ports. In this circuit, one address decoder for reading and two address decoders for writing are provided.
FIG. 7 is a diagram depicting a configuration of a conventional one read/two write SRAM circuit.
When reading data, a read address to indicate a read address position is first stored in a read address register RAR. The stored read address is supplied to a read column decoder RCDC and a read row decoder RRDC. The read column decoder RCDC and the read row decoder RRDC specify a row and a column of a read address position in a memory array 300 respectively. The data of the memory cell at the specified address position is output via an OR circuit 400.
When writing data to the one read/two write SRAM circuit, the two write addresses to indicate the two write positions respectively are stored in write address registers WAR1 and WAR2. The write address stored in the write address register WAR1 is stored in a write column decoder WCDC1 and write row decoder WRDC1. The write address stored in the write address register WAR2 is supplied to a write column decoder WCDC2 and write row decoder WRDC2. The two write column decoders and the two write row decoders specify the column and row at a write position on the memory array 300 respectively. To the two memory cells at the specified positions, the write data stored in the write data registers WDR1 and WDR2 are written via the write column decoders WCDC1 and WCDC2.
FIG. 8 is a diagram depicting a configuration of an SRAM cell used for a conventional one read/two write SRAM circuit. The conventional one read/two write SRAM cell comprises P-channel MOS transistors, N-channel MOS transistors, bit lines and word lines.
A P-channel MOS transistor 101 and an N-channel MOS transistor 102 are connected between the same two nodes, and constitute an inverter circuit. In the same way, a P-channel MOS transistor 103 and an N-channel MOS transistor 104 are connected between the same two nodes, and constitute an inverter circuit. A flip-flop circuit comprises of these four transistors using a loop of two inverter circuits, where one bit information is held.
An N-channel MOS transistor 105, the gate of which is connected to a read word lines +RWL, connects a read bit line +RBL and the node at the gate side of the transistors 101 and 102 constituting the inverter circuit. An N-channel MOS transistor 106, the gate of which is connected to a write word line +WWL0, connects a write bit line +WBL0 to the node at the gate side of the transistors 101 and 102 constituting the inverter circuit. An N-channel MOS transistor 107, the gate of which is connected to a write word line +WWL1, connects a write bit line +WBL1 to the node at the gate side of the transistors 101 and 102 constituting the inverter circuit.
An N-channel MOS transistor 108, of which gate is connected to the read word line +RWL, connects a read bit line −RBL to the node at the gate side of the transistors 103 and 104 constituting the inverter circuit. An N-channel MOS transistor 109, the gate of which is connected to a write word line −WWL0, connects a write bit line −WBL0 to the node at the gate side of the transistors 103 and 104 constituting the inverter circuit. An N-channel MOS transistor 110, the gate of which is connected to the write word line +WWL1, connects a write bit line −WBL1 to the node at the gate side of the transistors 103 and 104 constituting the inverter circuit.
When data is written to this SRAM cell, the write word line +WWL0, specified by the write row decoder WRDC1, is set to High state (hereafter H). By this, the N-channel MOS transistors 106 and 109 turn ON. Then the target data stored in the write data register WDR1 is input by the write column decoder WCDC1 via the specified write bit line +WBL0. At the same time, the opposite state of the write bit line +WBL0 is input via the write bit line −WBL0.
If the data to be stored is H, the N-channel MOS transistor 102 and the P-channel MOS transistor 103 turn ON, the node at the gate side of the transistors 101 and 102 constituting the inverter circuit is fixed to H, and the node at the gate side of the transistors 103 and 104 constituting the inverter circuit are fixed to Low state (hereafter L).
Data can be simultaneously written to this SRAM cell using a port of another system. In this case, the word line +WWL1 specified by the write row decoder WRDC2 is set to H. By this, the N-channel MOS transistors 107 and 110 turn ON. Then the target data to be stored in the write data register WDR2 is input by the write column decoder WCDC2 via the specified bit line +WBL1. At the same time, the opposite state of the bit line +WBL1 is input via the bit line −WBL1.
If the data to be stored is L, the N-channel MOS transistor 104 and the P-channel MOS transistor 101 turn ON, the node at the gate side of the transistors 101 and 102 constituting the inverter circuit is fixed to L, and the node at the gate side of the transistors 103 and 104 constituting the inverter circuit are fixed to H. By simultaneously writing data to different cells using the two systems, the write speed can be increased. In this case, hardware to prohibit the two systems from simultaneously writing a same position is necessary.
When data is read from this SRAM cell, the read word line +RWL selected as a result of decoding by the read row decoder RRDC is set to H. By this, the N-channel MOS transistors 105 and 108 turn ON. Then the data stored at the gate side of the transistors 101 and 102 constituting the inverter circuit, which is a part of the loop of the flip-flop circuit, is output from the read bit line +RBL specified by the read column decoder RCDC. At the same time, the opposite state of the read bit line +RBL is output from the read bit line −RBL by the inverter circuit inverting the state of the read bit line +RBL.
In the case of this one read/two write SRAM circuit, the number of write ports is double the number of read ports, so the data width is different between the data to be input and the data to be output. By simultaneously writing different cells using two systems, the data write speed can be virtually increased to double, and [the SRAM circuit] is used as a buffer circuit of which data write speed and data read speed are different.
FIG. 9 is a diagram depicting an example of using the one read/two write SRAM circuit. A central processing unit (hereafter CPU) 100 outputs the data D1 acquired by computation to a one read/two write SRAM circuit 101a. For fast computation, the CPU 100 is demanded to immediately output the acquired data and start another computation.
Hence the one read/two write SRAM circuit 101a receives the data using the two write ports, and outputs the data D2 via one read port. Since the number of read ports is ½ the number of write ports, the virtual transfer speed required for reading the data D2 becomes ½ the transfer speed required for writing the data D1.
A one read/two write SRAM circuit 101b receives the data D2, which is an output of the one read/two write SRAM circuit 101a, and write the data using two write ports. The written data D2 is read by one read port, and is output as data D3. Since the number of read ports is ½ the number of write ports, the virtual transfer speed required for reading the data D3 becomes ½ the transfer speed required for writing the data D2. As a result, the transfer speed required for reading the data D3 becomes one fourth the transfer speed required for writing the data D1.
In this way, the data, which is output from the CPU, gradually decreases the transfer speed. Since the data D1, which is output from the CPU, is not output very frequently, the speed may drop after the processing to receive the data D1 is executed as fast as possible. This way the CPU can perform a kind of release processing, that is, outputting data without waiting for an end of slow processing of the memory circuit in subsequent stages of the data D3.
Non-patent Document 1: “Niel H. El Weste, Kamran Eshraghi, “Principle of CMOS VLSI design from a system point of view”, issued by Maruzen Co., Ltd, pp. 310, 1988
However in the case of a conventional one read/two write SRAM circuit, which writes data at double speed by providing two write ports, one read address register and two write address registers are required. In the same way, one read address decoder and two write address decoders are required. Since these circuits are installed to be redundant, decreasing the size of a conventional one read/two write SRAM circuit is difficult.
Also in the one read/two write SRAM circuit, many word lines and transistors are used, which increases the memory cell size. Therefore the bit lines and the word lines become long, and resistance and wiring capacity increase. If resistance and wiring capacity increase, the drive current for driving the transistors decreases (since an increase in wiring capacity increases the load to be driven by the transistors), and it is difficult to increase the speed of the one read/two write SRAM circuit.